This invention relates to programmable look-up tables (LUTs) that have less leakage current than those in the prior art.
The logic cells that comprise a programmable logic device (PLD) often use programmable look-up tables (LUTs) as a means of implementing logic functions. (See, for example, Jefferson et al. U.S. Pat. No. 6,215,326.) These LUTs typically have N inputs that control a 2N-input multiplexer (mux), with 2N programmable static RAM bits, each feeding one of the 2N inputs of the mux. This allows the LUT to implement any combinational logic function of the N inputs. Typically, to avoid RAM-disturb issues, the output of each RAM feeding the LUT will be buffered with an inverter before feeding the input to the LUT. The 2N-input mux is typically created out of either an NMOS or full CMOS tree (e.g., FIGS. 1 and 2 herein, respectively). The CMOS tree (e.g., FIG. 2) has the advantage that the output of the LUT experiences a full voltage swing, while the NMOS mux (e.g., FIG. 1) has a Vt threshold voltage drop when the output is high, and thus may require a level-restorer on its output.
As CMOS processes have scaled down, transistors that would normally be “off” have begun to leak current. Whenever an off-transistor has its source and drain tied to different voltages, there is the potential for leakage current. In the examples shown FIGS. 1 and 2, the “off” transistors that may leak current have arrows pointing toward them. In devices with millions of transistors, this leakage current can add up to a large amount of stand-by power consumption. The invention described herein reduces the number of leaking transistors in the LUT, thus reducing the DC power consumption of the programmable device.